The Peripheral Component Interconnect Express (PCIe)™ interface protocol a standard across the computer industry for a high-speed data communication link. The performance of some PCIe devices can be constrained by form factor (e.g., the number of transmit vs receive lanes).
PCI Express (PCIe) is a protocol that describes buses for high speed interconnection between a host device (e.g., a CPU) and an I/O device (aka, a peripheral device, e.g., a solid state memory). Although PCIe has evolved from Gen1 (2.5 Gbps) to Gen3 (8 Gbps), the need for more bandwidth remains. The higher bandwidth requires more PCIe lanes, resulting in higher signal count connectors and cables which is more expensive. In applications where there is mechanical constraint of maximum signal count, the PCIe lane count is limited, and bandwidth is capped.
Like reference numbers and designations in the various drawings indicate like elements.